1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device that performs a data write operation and a data read operation.
2. Description of the Related Art
Generally, semiconductor devices including a Double Data Rate Synchronous Dynamic Random Access Memory Device (DDR SDRAM) device store an external data in a memory cell through a write operation or outputs a data stored in a memory cell to the outside through a read operation.
FIG. 1 is a block diagram illustrating a typical semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a first memory cell array 110_1, an Nth memory cell array 110_N, a read sense amplifier 120, a data pad 130, a write driver 140, and an enable signal generator 150.
A plurality of memory cell arrays including first to Nth memory cell arrays 110_1, . . . , 110_N are constituent elements for storing data, and they include a great deal of memory cells. Each memory cell may be selected by one word line and one column selection signal (not shown), and a data may be stored in a selected memory cell or a data stored in a selected memory cell is outputted according to the write operation and the read operation of the semiconductor memory device.
In FIG. 1, the first memory cell array 110_1 and the Nth memory cell array 110_N among the multiple memory cells are illustrated. Among a plurality of word lines coupled with the first memory cell array 110_1, a first word line WL1 is illustrated representatively, and among a plurality of word lines coupled with the Nth memory cell array 110_N, an Nth word line WLN is illustrated representatively.
The read sense amplifier 120 receives the data outputted from the first to Nth memory cell arrays 110_1, . . . , 110_N through primary/secondary data transfer lines IO and IOB during a read operation, sense-amplifies the data, outputs the sense-amplified data to the data pad 130. The write driver 140 receives the data transferred through the data pad 130 during a write operation, and drives the primary/secondary data transfer lines IO and IOB coupled with the first to Nth memory cell arrays 110_1, . . . , 110_N.
The enable signal generator 150 controls the enabling operations of the read sense amplifier 120 and the write driver 140 during the read and write operations. The enable signal generator 150 generates a read enabling signal EN_RD and a write enabling signal EN_WR in response to an internal command pulse signal BYPREP. Herein, the internal command pulse signal BYPREP is a signal enabled in response to an external read command or an external write command. The read enabling signal EN_RD is a signal for controlling the enabling operation of the read sense amplifier 120, and the write enabling signal EN_WR is a signal for controlling the enabling operation of the write driver 140.
FIG. 2 is a waveform diagram describing a read operation of the semiconductor memory device shown in FIG. 1. For the sake of convenience in description, a data corresponding to a first word line WL1 and transferred the read sense amplifier 120 is referred to as a first data IO/IOB@WL1, and a data corresponding to an Nth word line WLN and transferred the read sense amplifier 120 through the primary/secondary data transfer lines IO and IOB is referred to as an Nth data IO/IOB@WLN.
As illustrated in FIG. 1, a plurality of memory cell arrays are disposed between the first memory cell array 110_1 and the Nth memory cell array 110_N. This signifies that the first memory cell array 110_1 and the Nth memory cell array 110_N are disposed apart from each other, and also the primary/secondary data transfer lines IO and IOB are disposed longitudinally corresponding to the first memory cell array 110_1 and the Nth memory cell array 110_N. Therefore, the moment that the first data IO/IOB@WL1 arrives at the read sense amplifier 120 after the first word line WL1 is enabled and the moment when the Nth data TO/IOB@WLN arrives at the read sense amplifier 120 after the Nth word line WLN is enabled are different.
Referring to FIGS. 1 and 2, the first memory cell array 110_1 is disposed farther than the Nth memory cell array 110_N from the read sense amplifier 120. Thus, the Nth data IO/IOB@WLN is transferred to the read sense amplifier 120 earlier than the first data IO/IOB@WL1, and the first data IO/IOB@WL1 is transferred to the read sense amplifier 120 later than the Nth data IO/IOB@WLN.
Meanwhile, the enabling moment of the read enabling signal EN_RD enabled during a read operation is generally designed based on the data that is transferred latest to the read sense amplifier 120. In other words, the enabling moment of the read enabling signal EN_RD is designed based on the first data IO/IOB@WL1 that is transferred latest to the read sense amplifier 120. Therefore, the Nth data IO/IOB@WLN, which is transferred earliest, comes to have a reduced margin with an enabling control signal CTR_AT.
As the semiconductor memory devices are being integrated higher and higher, the number of memory cell arrays for storing data is increasing more and more. The increasing number of memory cell arrays signifies that the transfer time difference between the data transferred to the read sense amplifier 120 is becoming greater, and as illustrated in FIG. 2, the increase in the transfer time difference deteriorates the margin between the read enabling signal EN_RD and the data transferred earliest.